Question 2 of 5 · senior level

What is an instruction set architecture? CISC vs RISC, and why does x86 vs ARM matter to a software team in 2026?

🎤 Say this first

The ISA is the contract between compiled software and silicon: the instructions, registers and memory model a CPU promises to honor — implementations (microarchitectures) vary wildly beneath it. CISC (x86): many complex, variable-length instructions — decoded internally into RISC-like micro-ops since the Pentium Pro, so 'CISC vs RISC' converged inside the chip. RISC (ARM, RISC-V): fixed-size simple instructions, load/store architecture, easier to decode wide. Why you care now: ARM in cloud (Graviton/Axion) and laptops means multi-arch images, and — the sharpest software-visible difference — ARM's weaker memory model makes latent concurrency bugs that x86's strong ordering silently forgave actually fire.

The full picture

Contract layering: ISA stability is why a 1995 binary runs on a 2026 Xeon; microarchitecture freedom (pipelines, caches, OoO) is where 30 years of speedups came from — the cleanest example of interface-vs-implementation in all of computing, and worth saying exactly that way.
The real modern differences: fixed-length decode lets ARM designs go very wide (Apple's 8+ decoders vs x86's laborious variable-length decode); x86 carries decades of compatibility mass; both are micro-op machines behind the curtain.
Memory model, the practical landmine: x86-TSO ≈ only store→load reordering visible; ARM allows much more. Code missing a volatile/fence can run for years on x86 and break on Graviton — 'we migrated to ARM and found our data race' is a real 2020s genre. JMM-correct code is safe on both; that's the point of the JMM.
Team-level checklist for ARM adoption: multi-arch CI/images (buildx), re-run perf baselines (different cache/NUMA shapes), verify native deps/agents ship arm64, and price/perf test — Graviton's ~20–40% price-perf is why this stopped being optional.

🔄 Likely follow-up questions

What is x86-TSO, concretely, and which reordering does it still allow?
What does RISC-V's openness change for the industry?
What broke (or didn't) when your stack moved to Graviton — walk through the audit.