What is a bus? How do the CPU, memory and devices actually talk to each other in a modern machine?

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A bus is a shared pathway carrying address ('where'), data ('what') and control ('when/what kind') signals. The classic single shared bus is history: modern machines are a network — cores talk to caches over on-die interconnects (ring/mesh), the integrated memory controller drives DRAM over dedicated channels (DDR5, ~50–100GB/s/socket), and devices hang off PCIe, which is point-to-point serial lanes (x1/x4/x16) — really a tiny packet-switched network with lanes, not a party line. 'The bus' survives as a mental model; the reality is routed fabrics at every scale.

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Address/data/control decomposition still explains everything: a memory read = address out, control says 'read', data comes back; bus width (64-bit data) and clock set bandwidth — the vocabulary transfers to every interconnect since.
Why shared buses died: one talker at a time (arbitration), electrical loading limits speed as devices attach — the same reasons Ethernet hubs gave way to switches; point-to-point + switching won in both worlds. That parallel is worth saying out loud.
PCIe numbers that matter: ~2GB/s per lane per direction (gen4), ~4GB/s (gen5); an x16 GPU slot ≈ 32–64GB/s; an x4 NVMe drive ≈ 8–16GB/s. When someone asks 'why is GPU transfer the bottleneck' or 'can this box push 200Gbps', these are the arithmetic inputs.
Bandwidth budget thinking: memory channels, PCIe lanes and inter-socket links are shared budgets — a NIC and NVMe array can contend for the same lanes/memory bandwidth; 'the machine' is a network with links you can saturate one by one.

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